FIELD: information technology.
SUBSTANCE: LINK-port switch has N LINK-ports, N LINK-port controllers, a switch matrix, a block of resistors, an address allocation protocol decoder, a replay message generator, a comparator circuit, a constant, a LINK-port counter, an RCP-2 former, each LINK-port further includes an input LINK-port, an input buffer register, an input LINK -port, a counter for selecting the input port, an allocation time-out counter, a comparator circuit, a constant, each LINK-port controller further includes a TL field modification unit, two JK flip-flop, three OR elements, FIFO buffer memory, a control state machine, a state register, ROM1 for the switching table, a multiplexer, a comparator circuit, a constant, ROM2, five AND elements, an odd number control unit, a word counter, a control sum storage, a first heading register, a third heading word register, a unit for checking heading words.
EFFECT: switching data presented in form of bytes, provision for plurality of message delivery paths, prevention of ringing, prevention of message blocking.
7 cl, 28 dwg
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Authors
Dates
2010-11-27—Published
2009-05-04—Filed