PARALLEL COMPUTING CIRCUIT WITH PROGRAMMABLE ARCHITECTURE Russian patent published in 2013 - IPC G06F11/16 G06F15/16 

FIELD: information technologies.

SUBSTANCE: parallel computing system with programmable architecture (hereinafter referred to as PCS), comprising the first, second, third and fourth microprocessors, main memory, permanent memory, the first and second groups of PCS inputs are connected with the first group of inputs of the system controller and the first groups of inputs of the first, second, third and fourth microprocessors, differing by the fact that the PCS additionally includes the second, third and fourth permanent memories, the second, third and fourth, fifth and sixth main memories, a system controller, the first, second, third and fourth transceivers LVDS, the first, second, third and fourth transceivers Fibre channal TLK 1201, a controller LINK Fibre channal, a generator for 106.25 MHz, a generator for 10 MHz, a generator for 40 MHz, a unit of reset by power, a controller LINK MKO, the first and second transceivers MKO HI-1574, the first LINK switchboard, the second LINK switchboard and appropriate links between PCS units.

EFFECT: improved efficiency.

17 cl, 57 dwg