FIELD: information technology.
SUBSTANCE: apparatus includes a logic unit with a clock signal input and eight data inputs, a 64 bit FIFO register, whose inputs are connected to corresponding inputs of the computer system bus controller, which is connected to the system bus. The logic unit includes a multiplexer, a latch register with 448 cells, an adaptive demultiplexer, 8 data stream distributors, a control unit, wherein the output 64-bit bus of the multiplexer is connected to the corresponding input bus of the FIFO register. Outputs of the latch register are combined into 64 bit buses, which are connected to corresponding inputs of the multiplexer, and outputs of the latch register are connected to inputs of the adaptive demultiplexer, 32 outputs of the data stream distributors are connected to 32 inputs of the adaptive demultiplexer, and inputs of the distributors are connected to corresponding data inputs. A clock signal is transmitted to one input of the control unit and a signal which corresponds to the number of input channels, which varies from 1 to 8, is transmitted to the other input.
EFFECT: repacking data for any number of input streams from 1 to 8 without the need for strict synchronisation of output streams on clock frequencies.
3 dwg
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Authors
Dates
2011-03-20—Published
2009-09-17—Filed