FIELD: electricity.
SUBSTANCE: operational amplifier (OA) comprises an input chain of level shift (1), the input of which is connected to a non-inverting input (2) of OA, the first output is connected to a base of the first n-p-n transistor (T) (3), and the second output - to a base of the first p-n-p T (4) and to the first output of the first current source (CS) (5), the second output of which is connected to a negative supply bus (SS) (6) and to a terminal of supply of the first current mirror (CM) (7), the input of which is connected to a collector of T (4), the emitter of which is connected to an inverting input (8) of OA and to the emitter of T (3), the collector of which is connected to the input of the second CM (9), the terminal of supply of which is connected to the bus of the positive SS (10) of OA and to the first output of the second SS (11), the second output of which is connected to the base of T (3), the first output of CM (7) is connected to the first output of CM (9) and to the first input of the buffer (12), the output of which is connected to the output (13) of OA, the second input is connected to the second output of CM (7), and the third input - to the second output of CM (9). The following components are introduced: the second n-p-n T (14), the base of which is connected to the base of T (3); the second p-n-p T (15), the base of which is connected to the base of T (4), and the emitter is connected to the emitter of T (14); the third CM (16), the supply terminal of which is connected to the SS bus (6), and the first input - to the collector of T (15); an additional buffer (17), the first input of which is connected to the first output of CM (16), and the second input is connected to the second output of CM (16); the fourth CM (18), the supply terminal of which is connected to the SS bus (10), the input is connected to the collector of T (14), the first output is connected to the first output of CM (16), and the second output is connected to the third input of the buffer (17); the third and fourth n-p-n T (19) and T (20), accordingly, emitters of which are connected to the third output of CM (16), and bases are connected to the output of the buffer (17), the collector of T (19) is connected to the input of control of CM (18), and the collector of T (20) is connected to the input of control of CM (9); the fifth and the sixth n-p-n T (21) and T (22), collectors of which are connected to the SS bus (10), bases are connected to the output of the buffer (12), and emitters are connected to the third output of CM (16); the third and the fourth p-n-p T (23) and T (24), bases of which are connected to the output of the buffer (17), the emitters are connected to the third output of CM (18), the collector of T (23) is connected to the input of control of CM (16), and the collector of T (24) - to the control input of CM (7); the fifth and the sixth p-n-p T (25) and T (26), the emitters of which are connected to the third output of CM (18), the bases are connected to the output of the buffer (12), and the collectors are connected to the bus of the negative SS (6).
EFFECT: improved accuracy.
7 dwg
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Authors
Dates
2011-12-10—Published
2010-07-22—Filed