FIELD: information technology.
SUBSTANCE: parallel associative memory for searching all addresses at the same time and determining whether or not the same data as input data are stored, comprising parity generation means for generating a parity bit of n-bit data input at write time and search time, and a plurality of memory locations corresponding to a plurality of addresses; wherein each of said memory locations comprises n associative memory cells for storing n-bit data; a parity memory cell for storing the parity bit; a parity check means for determining whether or not the parity bit generated by said parity generation means at the search time and the parity bit stored in said parity memory cell are matched, and activating a parity match signal if there is a match; a word match detection circuit for activating a word data match signal if the n-bit data match; and a parity validation means; wherein the parallel associative memory further includes a parity error detection means.
EFFECT: high rate of parity checking input and stored data.
2 cl, 13 dwg
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Authors
Dates
2013-11-10—Published
2009-08-04—Filed