INTERNALLY UPDATED FLUSHING MEMORY MATRIX Russian patent published in 2004 - IPC

FIELD: flushing memory matrix and its internal updating. SUBSTANCE: flushing memory operating process includes following operations: selection of line to be updated in flushing memory matrix, erasing of this line, programming of this line, generation of address increment of mentioned line to be updated in flushing memory matrix. As an alternative, operating process can include following operations: read-out of chosen line in flushing memory matrix and saving of status of bit retrieved from mentioned chosen line, erasing of this line in flushing memory matrix, programming of this line in flushing memory matrix, and setting of mentioned chosen bit to first status in case status saved during first operation is first status. In this way one line of memory location can be updated after every N erasing and programming operation executed for flushing memory matrix. EFFECT: enhanced reliability of updating memory location lines for flashing memory matrix. 6 cl, 13 dwg