JFET TRANSISTOR SERIAL CONNECTION DIAGRAM Russian patent published in 2015 - IPC H03K17/10 

FIELD: radio engineering, communication.

SUBSTANCE: invention relates to electronic circuitry, and more specifically, to a switching device with serial connection of JFET transistors. The device contains at least two JFET transistors, connected in series (J₁-J₆) (field p-n junction FETs). The lowest of these (J₁) is connected to the first output (1) either directly or in cascade via a control switch (M). The device also contains at least one complementary JFET (J₂-J₅), and JFET (J₆), which is the most distant one from the lowest JFET (J₁) and therefore is called the uppermost JFET (J₆), connected to the second output (2) via a drain link. There is a stabilising circuit (D₁₁-D₅₃) connected between JFET (J₁-J₆) gates and the first output (1). There is also a complementary circuit connected between the gate output (G₆) of the uppermost JFET (J₆) and the second output. This circuit serves to correct the potential at the gate output (G₆) of the uppermost JFET (J₆) to the potential at the drain output (D₆) of the same JFET (J₆).

EFFECT: higher switching device reliability due to equal load onto gate outputs, which influences the dynamic distribution of the locking voltage.

9 cl, 4 dwg