FIELD: physics, computer engineering.
SUBSTANCE: invention relates to functional capabilities of commands of a computer system processor. Described is a separate loading/storage command upon execution of which a central processing unit accesses operands from two separate memory cell and condition code indicators are set, which indicate whether inseparable access to two operands has been performed through block-parallel disabled selected access to operands without intermediate operations for accessing a storage device from other central processing units. When using said command in the form of separate loading of a pair, loading is the access and separate data are stored in general registers.
EFFECT: high efficiency of executing inseparable operations.
16 cl, 19 dwg
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