FIELD: physics, computer engineering.
SUBSTANCE: invention relates to computer engineering. A memory controller comprises a plurality of ports, wherein each port is connected to receive memory operations from one or more sources, and wherein each port is dedicated to memory operation traffic of a particular type, wherein the memory controller comprises an agent interface unit configured to switch memory operation traffic from the plurality of ports to a plurality of memory channel units in response to relative quality of service (QoS) parameters for the memory operations, and where in response to receiving a first memory operation from a first source that has transmitted one or more previous memory operations and further in response to a first QoS parameter corresponding to the first memory operation indicating a higher level of service than previous QoS parameters corresponding to the previous memory operations, the memory controller is configured to upgrade the previous QoS parameters to the level of service indicated by the first QoS parameter.
EFFECT: optimising memory throughput.
17 cl, 22 dwg
