FAIL-SAFE RANDOM ACCESS MEMORY Russian patent published in 2016 - IPC G11C29/00 G06F11/07 

FIELD: computer engineering.

SUBSTANCE: invention relates to computer engineering. Fail-safe random access memory using linear code, having minimum number of digits, for single and double error detection, as well as to determine configuration of erroneous discharges and their correction value of error syndrome and response analysis results, produced based on of supply of test input source contains computing channel, excess computing channel, first decoder, corrector, first to seventh blocks of OR elements, first to third OR elements, first through fourth delay elements, first and second units of AND elements, RS-trigger, register, first through fourth blocks of nonequivalence elements, second decoder, NOT element, storage unit and unit for calculating correction feature, at that, additionally contains eighth unit of OR elements, third unit of AND elements, first encoding device, unit for calculating syndrome, second encoding device.

EFFECT: technical result consists in reduction of information and hardware redundancy owing to use of linear code.

1 cl, 2 dwg, 1 ex