FIELD: computing technology.
SUBSTANCE: group of inventions relates to computer engineering and can be used to control processors using redundancy. System comprises a pair of processors with at least two processors and/or processor cores that are redundant, comparator for checking synchronisation status of processors and detecting synchronisation error, at least one peripheral unit, at least one switching array, which is capable of allowing or blocking access to processors of pairs of processors or access of said processors of pairs processors to said peripheral unit, an error processing unit which is configured to receive signals of two comparators and control said switching array for complete or selective prevention of access of the processor, or core, or pair of processors to at least one memory and/or said peripheral units, wherein said pair of processors in error-free operating mode can execute different programs for providing functions, and in case of error a pair of processors that does not contain an error, assumes at least some functions of the pair processors containing an error.
EFFECT: technical result is high noise immunity.
32 cl, 24 dwg
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Authors
Dates
2016-05-27—Published
2011-03-18—Filed