FAULT-TOLERANT MEMORY UNIT Russian patent published in 2017 - IPC G11C29/52 G06F11/07 

FIELD: information technologies.

SUBSTANCE: method is implemented by encoding of the source binary information based on organizing of independent examinations and due to introduction of an input encoding unit, an output coding unit, an error detection unit, a first OR gate, a second OR gate, AND gate array block, a first AND gate, a second AND gate, a first trigger, a second trigger, NOT gate, a delay element, a "device failure" transparency.

EFFECT: provision of fault-tolerance by distinguishing between intermittent and constant errors.

1 dwg, 2 tbl