FIELD: radio engineering, communication.
SUBSTANCE: in the method, input/output/memory access areas of the CPCI bus are defined, the STOP data transfer stoplight is turned on when the CPCI bus accesses memory form, and the wait signal S_WAIT is turned on to wait for the ISA bus device to be ready when the CPCI bus accesses input/output form; to determine the actual SA address signal and the access mode for CPCI bus to access the ISA bus, ADDR_VLD signal of address resolution is used, reading enabling signal barx_rd, recording enabling signal barx_wr and enabling signal of S_CBE byte determine the latch signal of the BALE address of the ISA bus; the decision is made to the data count in bytes allowed in the 32-bit data, the reading/recording signal of the IOW/IOR device or the reading/recording signal of MEMR/MEMW memory device is determined in accordance with the signal pulse width that is determined by the ISA bus.
EFFECT: increase data transfer rate in the network.
4 cl, 5 dwg
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Authors
Dates
2017-05-16—Published
2015-05-20—Filed