FIELD: image processing means.
SUBSTANCE: group of inventions relates to display devices and discloses a latch control circuit and a shift register. Latch control circuit on the AND-NOT elements includes a set of cascade-connected latch shift registers on the AND-NOT element, each of the shift register circuits includes a clock transmission control circuit and a latch circuit on the AND-NOT elements. Clock transmission control circuit is triggered by the first clock pulse of the clock signal to transmit the control pulse of the previous level to the latch circuit on the AND-NOT elements, then the control impulse is latched by the latch circuit on the AND-NOT elements. Latch circuit on the AND-NOT elements is additionally triggered by a subsequent second clock pulse of the first clock signal for outputting a locked control pulse.
EFFECT: technical result is the implementation of the control circuit of the gate drive in accordance with CMOS technology and a reduction in power consumption.
15 cl, 5 dwg
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Authors
Dates
2018-12-25—Published
2015-01-28—Filed