PARALLEL PROBABILISTIC ADDER Russian patent published in 2018 - IPC G06F19/00 

FIELD: measuring equipment.

SUBSTANCE: invention relates to the field of automation and measurement technology. Parallel probabilistic adder includes an n-bit result counter, an n-bit result register, a K-bit counter for the number of tests, a pseudorandom uniformly distributed number generator, and a multiplexer for M Log₂Q control inputs, to which a random uniformly distributed signal comes from a generator of pseudo-random uniformly distributed numbers, and Q informational probability mappings of the terms are fed to the information inputs, the output of the multiplexer is connected to the input of the result counter, the parallel outputs of which are loaded on the parallel inputs of the result register of the same bitness, to the permitting input of which the output of the counter of the number of tests is connected, to the "shift to the left" input of the result register Log₂Q of shift pulses is consistently supplied, and the synchronization inputs of the counter of the number of tests and the generator of pseudorandom uniformly distributed numbers are supplied with a clock signal from the clock generator, and the output of the result register is the output of the entire circuit.

EFFECT: technical result is aimed at widening the range of tools for the same purpose.

1 cl, 1 dwg