REDUCING CAPACITOR VOLTAGE CONVERTER Russian patent published in 2019 - IPC H02M3/10 

FIELD: electrical engineering.

SUBSTANCE: invention relates to electrical engineering, can be used to convert DC voltage at input to DC voltage at output with voltage reduction in whole number of times. Lowering capacitor voltage converter comprises two key elements (1) and (2), two input terminals (3) and (4), two output terminals (5) and (6) and capacitor-diode stages, anode of first diode (8) of the first stage is connected through the first key element (1) to one of input terminals (3), first capacitor (9) of each stage, except the first and the last one, is connected to the anode of first diode (8) of its stage, the second plate of capacitor (9) in each stage, except for the last one, is connected to anode of second (10) and cathode of third (11) diodes of its stage, cathode of second diode (10) of each stage, except for the last one, is connected to the first coating of condenser (9) next step, cathodes of first diodes (8) of all stages, except for the last one, are combined, the first output of the second key element (2) is connected to one of output terminals (5), the anodes of third diodes (11) of all stages, except for the last one, are interconnected. Through resistor (12) anode of first diode (8) of first stage is connected to other input terminal (4), point of connection of third diodes (11) of all stages, except last, second coating of capacitor (9) of last stage and second output terminal (6). First capacitor (9) of the first stage is connected to the cathode of first diode (8) of its stage, first capacitor (9) of the last stage is connected to the first output terminal (5). Key elements are made in the form of field transistors, the source of the first of which is one output of the first key element (1), and drain is another output of first key element (1) and is connected to gate of second field transistor, source of which is second output of second key element (2), which is connected to cathode of first diode 8 of penultimate stage, and drain is first lead of second key element (2). Gate of the first field-effect transistor is clock input (13) of the device.

EFFECT: technical result is the device simplification and improvement of its efficiency.

1 cl, 2 dwg