FIELD: physics.
SUBSTANCE: invention relates to radio engineering and can be used in digital transmitters and receivers. Device comprises a memory area arranged in form of two identical K-bit shift registers with parallel output of information and with three output states, corresponding outputs of registers are combined into K common leads, which in pseudorandom order, according to rearrangement of leads, are connected to data inputs of multiplexer. Device also has a summing counter with a translation unit K, which counts two logic AND elements on the input bit frequency, a flip-flop operating in a counting mode.
EFFECT: technical result is reduction of delay and simplification of device implementation.
1 cl, 6 dwg
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Authors
Dates
2020-04-08—Published
2019-05-20—Filed