FREQUENCY-PHASE DETECTOR Russian patent published in 2020 - IPC H03D13/00 

FIELD: digital electronics.

SUBSTANCE: invention relates to digital electronics and can be used in phase locked loop (PLL) systems. Detector comprises six CMOS switches, two T flip-flops, JK flip-flop, logical element 2OR-NOT and logic element 2OR; wherein first input of device is connected to combined inputs of first, third and fifth CMOS switches; second input of device is connected to combined inputs of second, fourth and sixth CMOS keys; C-input of the first T-flip-flop is connected to combined outputs of the first and second CMOS switches; C-input of JK-flip-flop is connected to combined outputs of the third and fourth CMOS switches; C-input of the second T-flip-flop is connected to the combined outputs of the fifth and sixth CMOS switches; second output of device is connected to combined T-input of first T flip-flop, Q-output of JK flip-flop and C-input of third CMOS switch; second input of logical element 2OR-NOT is connected to combined J-input of JK-flip-flop, nQ-output of second T flip-flop and C-input of the sixth CMOS switch; first input of logic element 2OR-NOT is connected to combined K-input of JK-flip-flop, nQ-output of first T flip-flop and C-input of second CMOS-key; C-input of fourth CMOS switch is connected to combined T-input of second T-flip-flop, nQ-output of JK-flip-flop; first output of the device is connected to the combined Q-output of the first T-flip-flop and the C-input of the first CMOS switch; third output of device is connected to combined Q-output of second trigger and C-input of fifth CMOS-key; first input of logic element 2OR is connected to output of logical element 2OR-NOT; third input of device is connected to combined input of logic element 2OR and R-input of JK-flip-flop.

EFFECT: technical result consists in excluding the possibility of "capturing" coherent and multiple frequencies of the reference signal, which enables to avoid risks of failure in the mode of frequency detection, high stability of operation of the PLL circuit, high reliability, low power consumption.

1 cl, 7 dwg