FIELD: radio engineering and communication.
SUBSTANCE: group of inventions relates to the field of digital-to-analog conversion, in particular to implementations of a high-speed and low-power digital-to-analog converter with an increase in frequency. The device comprises a decoder circuit, the decoder circuit operating at a given sampling frequency, a mixer circuit connected to the decoder circuit and configured to combine each of the decoded parallel digital data bits with a conversion clock signal to obtain digital data bits with a frequency shift, which have a timing discrepancy with respect to each other, a synchronization circuit connected to the mixer circuit, providing a clock signal for the synchronization device and configured to time-align said digital data bits with a frequency offset in response to the clock signal for the synchronization device, and switching network connected to a timing device circuit.
EFFECT: technical result is to reduce the time discrepancy between the bits of parallel digital data in relation to each other.
20 cl, 15 dwg
