FIELD: computing technology.
SUBSTANCE: invention relates to computing technology and can be used in digital phase modulators. An accumulating adder-subtractor modulo random natural number, containing an n-bit adder, a multiplexer, and a register, as well as an (n + 1)-bit adder, the n lowest digits of the sum output whereof are bitwise connected with the first information input of the multiplexer, the second information input whereof is connected with the sum output of the n-bit adder, and the output of the multiplexer is connected with the information input of the register, the output whereof is connected with the input of the first term of the n-bit adder and is the information n-bit output of the apparatus, the clock input of the register is the clock input of the apparatus, and the zeroing input of the register is the zeroing input of the apparatus, wherein a logical zero is supplied to the transfer input of the n-bit adder and a logical unit is supplied to the transfer input of the (n+1)-bit adder, also an additional n-bit adder, a first and a second sets of inverters, as well as a second and a third n-bit multiplexers are included therein.
EFFECT: increase in the operating speed.
1 cl, 2 dwg
Title | Year | Author | Number |
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ACCUMULATING ADDER-SUBTRACTOR BY AN ARBITRARY NATURAL NUMBER MODULO | 2021 |
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Authors
Dates
2022-01-21—Published
2021-04-13—Filed