FREQUENCY SYNTHESIZERS SUMMING UNIT Russian patent published in 2021 - IPC G06F7/505 

FIELD: frequency synthesizers summing unit.

SUBSTANCE: invention relates to a summing unit for frequency synthesizers.

EFFECT: improves the processing speed of constant numbers. The summing unit contains an n-bit adder, a multiplexer and a register, as well as an (n+1)-bit adder, the n least significant bits of the sum output of which are bitwise connected to the first information input of the multiplexer, the second information input of which is connected to the sum output of the n-bit adder, and the output of the multiplexer is connected to the information input of the register, the output of which is connected to the input of the first term of the n-bit adder and is the information n-bit output of the device, the clock input of the register is the clock input of the device, and the input of zeroing the register is the input to zeroing the device, a logical zero is fed to the transfer input of the n-bit adder, and the input of its second term is the information n-bit input of the device, while an additional n-bit adder is introduced, the input of the first term is combined with the information input of the device, and the input of the second term is the bitwise inverted binary code of the module is fed, over which the summation is carried out, a logical unit is fed to the transfer input of the additional adder, and its output of the sum is bitwise connected to the n least significant bits of the input of the first term of the (n+1)-bit adder, the least significant n bits of the input of the second term of the (n+1)-bit adder are bitwise connected to the register output , in this case, a logical zero is supplied to the transfer input of the (n+1)-bit adder, as well as to the high-order bit of the input of its second addend, a logical unit is fed to the high-order bit of the input of the first term of the (n+1)-bit adder, and its high-order bit is the sum output is connected to the multiplexer control input.

1 cl, 2 dwg