FIELD: computing.
SUBSTANCE: invention relates to computing. A high-speed accumulating adder modulo an arbitrary natural number is characterized by the fact that an additional n-bit adder, as well as the second and third n-bit registers are introduced into it, and the clock inputs of the registers are connected to the clock input of the device, and the register zeroing inputs are connected to the zeroing input of the device, the output of the second n-bit register is connected to the input of the second term of the n-bit adder, and the information input of the second n-bit register is an n-bit information input of the device and is combined with the input of the first term of an additional adder.
EFFECT: performance improvement.
1 cl, 2 dwg
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Authors
Dates
2021-08-26—Published
2020-12-29—Filed