FIELD: computing technology.
SUBSTANCE: digital debugging complex integrated into the object under test connected to data, address and control buses of a computer, with a JTAG interface with TCK, TMS, TDO, TDI and TRST wire communication lines, and comprises a multiplexer (M), an instruction register (RI), and a data register (RD1), introduced wherein are a controller, a decoder (D), two multiplexer blocks (BM1 and BM2), two shift registers (RS1 and RS2), a comparator (C), a stop register (RO), an address register (RA), a one-bit register (OR), and two data registers (RD2 and RD3).
EFFECT: provided possibility of reprogramming, debugging computer hardware and software.
1 cl, 5 dwg, 4 tbl
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Authors
Dates
2022-06-07—Published
2021-01-11—Filed