FIELD: information technologies.
SUBSTANCE: microcomputer (ASIC) comprises multiple integral circuits (IC), which are connected to each other with interfaces that are synchronous to data sources. At first test data is input into trigger for data transfer (F1) and trigger for transfer of clock pulse (F2) into IC on the side of data transfer. Then circuit (11) of phase locking generates clock signal, in response to which the first and second triggers send test data and clock pulse. Triggers (F3, F4) for reception of IC data on the side of data reception, test data is registered, which come from the first trigger (F1) in compliance with clock pulse, which comes from trigger (F2).
EFFECT: provision of testing at working frequency at the level of circuit boards without application of system level test, and assessment of data sent along each transfer channel.
12 cl, 21 dwg
