FIELD: computing technology.
SUBSTANCE: described technical result is achieved by the logic module containing three AND elements, two OR elements, and eight majority elements, wherein the ith input of the jth majority element is connected with the ith inputs of the jth AND, OR elements, the second inputs of the (i+3)th and eighth majority elements and the output of the jth AND element are connected to the outputs of the (i+2)th and seventh and to the second input of the (4×(j-1))th majority element, respectively; the outputs of the jth, seventh, eighth majority elements and the jth input of the third AND element are connected with the third inputs of the (11-4×j)th, fourth, sixth majority elements and the output of the jth OR element, respectively; the third inputs of the fifth and eighth and the output of the third majority elements are connected to the output of the third AND element and to the first input of the eighth majority element, respectively, and the first inputs of the third and seventh and the first inputs of the fourth and fifth majority elements form, respectively, the first and second setting inputs of the logic module, the (i+3×(j-3))th, seventh information inputs and the output whereof which are connected with the ith input of the jth, the first input and output of the sixth majority elements, respectively.
EFFECT: implementation of simple symmetric Boolean functions depending on 7 input binary signals.
1 cl, 1 dwg
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Authors
Dates
2022-08-23—Published
2021-06-17—Filed