FIELD: computer engineering.
SUBSTANCE: invention relates to computer engineering and can be used in digital pipeline-type computing devices, as well as in frequency synthesizers and frequency dividers with fractional division factor and in cryptographic applications. Device contains 2n-bit and (n+1)-bit registers, where n is digit capacity of processed numbers, n-bit and (n+1)-bit adders, two multiplexers, a trigger, a demultiplexer, three information inputs of the device, a clock input of the device, two information outputs of the device.
EFFECT: broader functional capabilities of the device owing to implementation of accumulating summation of numbers by an arbitrary modulus in a two-channel mode for two successive streams of numbers.
1 cl, 1 dwg
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Authors
Dates
2024-07-30—Published
2024-03-01—Filed