MATRIX STORAGE UNIT FOR READ-ONLY MEMORY UNIT Russian patent published in 1995 - IPC

Abstract SU 1338688 A1

FIELD: computer engineering. SUBSTANCE: clearance buses are located over all information buses under floating silicon electrodes. In addition, field-effect transistors are connected to each information bus instead of a single information bus. This results in possibility to exclude injection of hot electrons from channel of storing transistor that was no selected. This is caused by voltage drop of open address field-effect transistor while capacitor is charged. As result, threshold voltage of storing transistor that was not selected is not changed. EFFECT: increased reliability. 1 dwg

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SU 1 338 688 A1

Authors

Ovcharenko V.I.

Portnjagin M.A.

Dates

1995-12-20—Published

1986-01-21—Filed