FIELD: computer engineering. SUBSTANCE: matrix storage circuit has semiconductor substrate 1 of first type of conductance, diffusion region 4 of first type of conductance, dielectric layers 5, 8, 10 and 12, discharge diffusion wires 2 and 3 of second type of conductance, erasing polysilicon wires 6, 7, polysilicon electrodes 9, address polysilicon wires 11. Section of address wire 11 located above polysilicon electrode 9, electrode 9 and discharge diffusion wire 3 form correspondingly first, second gates and source of memory transistor. Advantage of this matrix storage circuit lies in increase of its reliability thanks to positioning of erasing polysilicon wires on surface of fourth dielectric layer located on layer of semiconductor of first type of conductance and in butts on one of sides of discharge diffusion wires of second type of conductance. As a result key enhancement-mode MIS transistors with invariable threshold voltage are formed under erasing wires which enables erasure of information to be conducted before emergence of negative threshold voltages of memory transistors without change of serviceability of storage circuit. EFFECT: increased reliability of storage circuit. 1 dwg
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Authors
Dates
1994-12-30—Published
1986-06-04—Filed