FIELD: electronics. SUBSTANCE: invention relates to logic integrated circuits with matrix arrangement of elements. Mainframe matrix device has units of matrix cells on which periphery units of buffer cells are placed which are designed for realization of high-power output stages. Units of cells of control aid are inserted between units of buffer cells and units of matrix cells. Cells of control aid have four series networks of MIS transistors of different configuration. Two of them are built on transistors of first type and two others - on transistors of second type. EFFECT: reduced rate of growth of current in buffer stage, of interference voltage and of peak consumption current. 2 cl, 4 dwg
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Authors
Dates
1994-07-15—Published
1989-04-19—Filed