MAGNETIC-CONTROL LOGICAL GATE Russian patent published in 1997 - IPC

FIELD: microelectronics, integral circuits, memory gates. SUBSTANCE: device has first-type semiconductor substrate, eight doped second-type regions, which pairs provide drain and source regions of four field-effect transistors. substrate surface is covered with dielectric film which has holes over drain and source regions. In addition device has eight conducting contact regions which are located above drain and source regions on surface of said regions and surface of dielectric film. In addition device has four conducting gate regions, which are located on surface of dielectric film between corresponding drain and source regions of each transistor. In addition device has four current lines, which are located on surface of dielectric film. First current line is in contact with source regions of first and second transistors and serves as supply line; second current line is in contact with source and gate regions of third and fourth transistors and serves as supply line; third line is in contact to gate of first transistor and drain regions of second and fourth transistors and serves as output line; fourth line is in contact to gate of second transistor, source regions of first and third transistors and serves as output line. In addition device has dielectric region which is hidden in substrate, insulating region which is located around hidden dielectric region and contacts it and dielectric film, four heavily-doped first-type regions, which contact insulating region and hidden dielectric region and are located in pairs in symmetry at opposite sides of first-type region, which consists of dielectric region and insulating region. In addition device has four contacts to heavily-doped first-type regions. They are connected by means of current strips with power supply lines and output lines so that first strip is connected to power supply line and contact to one of heavily doped first type region; second strip is connected to another power supply line and opposite contact of heavily doped first type region; third strip is connected to output line and contact of second pair of heavily doped first type regions; fourth strip is connected to opposite contact of second pair of heavily doped regions and to another output line. EFFECT: increased functional capabilities. 3 dwg