MODULO-FIVE ADDER Russian patent published in 1994 - IPC

FIELD: automation and computer engineering. SUBSTANCE: device has three prohibition gates, five AND gates, OR gate, majority gate with threshold value 3, three modulo-two adders, six inputs, three outputs. Complexity of adder equals to 48. Adder speed, which is determined by circuit depth, equals to 22τ where t is delay per gate. Binary variables X₁, Y₁, X₂, Y₂, X₃, Y₃ which represent first, second and third bits of added values X and Y enter device inputs. Logical functions Z₁, Z₂, Z₃ are generated at output where Z₁ is first bit, Z₂ is second bit, Z₃ is third bit of value Z and Z = X + Y (mod 5). EFFECT: increased functional capabilities. 1 dwg