MODULO 5 ADDER Russian patent published in 1994 - IPC

FIELD: computer technology; automatics. SUBSTANCE: adder has five INHIBITION gates, three AND gates, majority element, which has threshold to be equal to three, two MODULO 2 ADDITION gates, EXCLUSIVE-OR gate, six inputs and three outputs. Complexity of the adder according to number of inputs is equal to 45, high speed of operation, defined by depth of the circuit, is equal to 22τ, where t is rectifier delay. Binary variables (x₁,y₁, x₂,y₂, x₃y₃) enter inputs of the device, which have to be the first, the second and the third digits of operands to be added X and Y correspondingly. Logic functions z₁, z₂, z₃ are realized at outputs of the adder, where z₁ is the first digit, z₂ is the second digit, z₃ is the third digit of Z operand and Z=X+Y(mod 5). EFFECT: high speed of operation; wide functional capabilities. 1 tbl, 1 dwg