FIELD: computer engineering. SUBSTANCE: device has data buffer register, syndrome calculator, control and synchronization unit, first and second coded word character counters, erase flag counter, locator generator, circuit controlling recording of numbers of erased characters and their locators, number-of-flanges decoder, register file of erased character numbers, first and second decision units, erasure unit, error detection and definition unit, number-of-erased-characters register, first, second, and third data commutators, number-of-corrected-characters counter, decoder, error value register file, correction control unit, error value buffer, m-bit modulo q adder, AND gate. EFFECT: improved speed and implementation of two modes of device operation due to concurrent execution of two algorithms (correction and correction, including erased characters); facilitated variation of decoding strategy and prediction of failure before decoding due to introduction of decision units; provision for checking device in the course of decoding, in addition to prediction of number of errors, due to introduction of corrected error counter. 5 cl, 10 dwg, 5 tbl
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Authors
Dates
1995-05-27—Published
1993-03-03—Filed