PHASE SHIFT MEASUREMENT METHOD AND DEVICE FOR ITS REALIZATION Russian patent published in 1997 - IPC

FIELD: measurement technology. SUBSTANCE: phase shift measurement method is based on digitization of measurement signal and its conversion to digital signal, on summation of codes and calculation of phase shift. Groups are formed of n samples of digitized measured signals taken in succession. In addition, single- or multi-digit digital signals are formed at 1/n digitization frequency. These signals depend on group of n samples of digitized measured signal and on group number of n samples of reference signal digital sine and cosine components which are supplied for summing-up of their codes. Device has analog-to-digital converter, the input of which is device input, and synchronization unit. First synchronization output of synchronization unit is connected to analog-to-digital converter. Device has also two series-connected storage adders, two storage registers and microprocessor computing unit. In addition, device is provided with shift register the data input of which is connected to output of analog-to-digital converter, synchronization input is connected to first synchronization output of synchronization unit. Device has auxiliary storage register the data input of which is connected to shift register output, storage device the first address input of which is connected to output of auxiliary storage register, and two data outputs are connected to data inputs of storage adders. Device has also second auxiliary storage register the data input of which is connected to data bus of microprocessor computing unit, and its output is connected to second address input of storage device. "Record" input is connected to "record" output of microprocessor computing unit. Device has counter, the data outputs of which are connected to third address input of storage device, and code presetting input is connected to auxiliary data output of storage device. Second synchronization output of synchronization unit is connected to synchronization inputs of storage adders, auxiliary storage register and counter, and third synchronization output of synchronization is connected to reset input of storage adders, to synchronization input of storage registers and to "interrupt inquiry input of microprocessor computing unit, and "read" output of microprocessor computing unit is connected to respective inputs of two storage registers. EFFECT: higher measurement results. 2 cl, 4 dwg