METHOD AND CONTROL CIRCUIT FOR DIGITAL-PROCESSING PHASE-LOCKED LOOP FOR NETWORK SYNCHRONIZATION Russian patent published in 2000 - IPC

FIELD: electronic engineering. SUBSTANCE: proposed control algorithm implies that when both reference clock signals are abnormal, fast or normal mode can be transferred to hold mode without changing preset reference phase deviation to recover normal tracking of clock signal in hold mode using as reference phase deviation the value obtained by subtracting mean value of phase deviation data in hold mode from that for preset time space upon transfer from hold to fast mode. EFFECT: provision for eliminating phase jump during mode-of-operation transfer. 7 cl, 7 dwg