FIELD: computer engineering, data processing. SUBSTANCE: device has global data bus, which provides connection of bus master circuit to bus slave circuits, address request signal line. Address words is subjected to transmission in next period instead of data word. Bus slave circuits may define limits in which they can keep packet mode transmissions and may send delay period request signal and combination of signals, which informs that packet transmission mode should be interrupted. EFFECT: increased number of data words combined into packets, increased speed of processing. 9 cl, 5 dwg
