MEMORY UNIT FOR STORING DATA AND PROCESSOR BUS Russian patent published in 1999 - IPC

FIELD: computer engineering. SUBSTANCE: device has central processing unit, which is connected to memory unit (for example, cash, RAM or disk storage) through single-direction reading bus and single-direction write and address bus. Reading bus and write and address bus are provided only in one direction. This results in possibility to eliminate deadlocks caused by alternating direction for reverse signal passing through bus. Data reading words and instruction-information words are transmitted from cash memory to CPU kernel through reading bus. Instruction-address words, address reading words and data reading words are multiplexed in times by writing and address bus for transmission from kernel to cash memory. System provides packet mode transmission. This results in decreased number of addresses to be transmitted through writing and address bus. EFFECT: increased speed of signal transmission due to bus separation, increased transmission rate through writing and address bus. 8 cl, 8 dwg