FIELD: digital data transmission systems, noise immune data protection systems using correction codes including cascade ones. SUBSTANCE: newly introduces in device are random-access memory, modulo two adder unit, number comparison unit, full adder, coincidence register, comparison unit, and synchronization counter. First output of decoder unit is connected to input of modulo two adder unit whose remaining inputs are connected to register outputs of second Haffmen filter; second output of decoder unit is connected to write enable input of random-access memory; outputs of modulo two adder unit function as inputs of number comparison unit whose other inputs are connected to more significant bits of counter; output of number comparison unity is connected to more significant bits of RAM address input whose less significant bits of address input are connected to less significant bits of counter; clock input of the latter is connected to synchronization input of device and also to clock input of synchronization counter whose setting inputs are connected to outputs of modulo two adder unit; enable input of synchronization counter is connected to threshold unit output; RAM output is connected to input of full counter whose second input is continuously placed at logical one; full adder output is connected to RAM data input and also to data input of coincidence register and to input of comparison unit whose second input is connected to coincidence register output; comparison unit output is connected to enable input of coincidence register whose output is also connected to threshold unit input; synchronization counter output is connected to enable input of sync pulse generator and also to synchronization output of device. EFFECT: enhanced noise immunity of device enabling its use in high-noise channels. 1 dwg
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Authors
Dates
2003-01-27—Published
2001-03-05—Filed