FIELD: digital data transfer systems; frame synchronization in noise-immune data protection systems using correcting codes, including concatenated ones.
SUBSTANCE: proposed device has delay register, error detection unit, decoder unit, modulo two adder unit, counter, random-access memory, threshold unit, full adder, OR gate, switching unit, digit sequence count circuit, digit comparison circuit, full digit adder, and register unit. Inputs of delay register and error detection unit are integrated and connected to data input of device; error detection unit is made in the form of two series-connected Huffman filters and syndrome register, each Huffman filter having series-connected register and modulo two adder; output of second Huffman filter is connected to input of syndrome register whose output is connected to input of decoder unit; output of the latter is connected to modulo two adder unit whose other input is connected to output of second Huffman filter register. Inputs of digit comparison unit are connected to counter high-order digits; output of digit comparison unit is connected to high-order digits of RAM address input; low-order digits of the latter are connected to those of counter; clock input of the latter is connected to synchronization input of device.
EFFECT: enhanced noise immunity, ability of operating in channels where noise level is high.
1 cl, 1 dwg
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Authors
Dates
2007-07-10—Published
2005-11-17—Filed