FIELD: pulse engineering. SUBSTANCE: flip-flop device has first and second NOR or NAND gates 1, and 2, respectively. First input of gate 1 interconnected with third input of gate 2 and first input of gate 2 are connected, respectively, to setting inputs 3, 4 of flip-flop device. Second input of gate 1 is connected to output of gate 2 and its output, to input of memory gate 5 whose output is connected to second input of gate 2. EFFECT: simplified circuit arrangement; reduced immunity to power interruption. 2 cl, 3 dwg
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