METHOD FOR POSITIONING SEMICONDUCTOR WAFERS IN COORDINATE READING SYSTEM OF INSTALLATION FOR THEIR ABRASIVE CUTTING INTO CHIPS Russian patent published in 2003 - IPC

FIELD: microelectronics. SUBSTANCE: prior to cutting wafer bearing grid on its surface virtual adjustment system is brought out to display device screen and its coordinates are adapted to project of tool cutting edge onto stage surface and also to project of stage turn axis onto this surface. To this end use is made of adjusting plate disposed on stage and the latter is displaced along X axis of coordinate reading system of installation, and cutting edge of tool is brought in contact with adjusting plate surface to form first cutting line. Then cutting edge of tool is brought in contact with adjusting plate surface for second time after stage is turned through 180 deg. to form second cutting line. After that intermediate line between cutting ones that functions as virtual adjusting system in the form of straight line with fixed reference point whose coordinates are adapted to projection of stage axis of turn onto its surface is visualized on display device screen. Display device is coupled through feedback circuit with each of computer television microscopes for matching and processing data on mentioned adjusting system visualized on display device screen. Adjusting system is coordinated with coordinate reading system of installation according to specified algorithm. Then wafer being treated is placed on stage and positioned with respect to coordinate reading system by bringing virtual adjusting system produced on device screen in alignment with grid line. All positioning processes are automated. EFFECT: enhanced positioning speed of separating tracks relative to cutting edge of tool; enhanced yield and labor productivity. 3 cl, 8 dwg