METHOD FOR DECREASING LOAD ON BUS IN SYNCHRONOUS DATA BUS SYSTEM Russian patent published in 2007 - IPC G06F13/40 

Abstract RU 2295149 C2

FIELD: technology for buffering between synchronization circuits realizing communication by means of global synchronous bus, in particular, can be used for decreasing load on bus in system of multiplexed bus with time division (TDM).

SUBSTANCE: in accordance to method, local TDM data bus is introduced as well as active buffer including logical circuit controlled by central processor, between loads of transmitter-receiver and TDM bus. Active buffers in direction of receiver and transmitter provide time delay for data outputted from first local TDM bus onto TDM bus of commutation plate and back onto second local TDM bus with precise duration of one TDM frame or integer number of TDM frames.

EFFECT: decreased signal degradation and bit error values.

13 cl, 5 dwg

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RU 2 295 149 C2

Authors

Vego Arild

Khellum Pol Longva

Mal'Vig Roar

Dates

2007-03-10Published

2002-12-27Filed