FIELD: information technologies.
SUBSTANCE: storing and restoration of computation process context in processor is two-staged. At the first stage the program counter and processor state counter values are automatically saved in context stack. At the second stage the required number of addressable context register groups is software saved. Processor operates with data memory segments through its own virtual file registers. And storing of base addresses of all virtual register files is performed by issuing just one command.
EFFECT: higher task context and procedure stepping rate with smaller amount of hardware resources used.
18 cl, 8 dwg
| Title | Year | Author | Number |
|---|---|---|---|
| PROCESSING ADMINISTRATION RELATED TO SELECTED ARCHITECTURAL FUNCTIONS | 2015 |
|
RU2665243C2 |
| INCREASING NUMBER OF GENERAL PURPOSE REGISTERS AVAILABLE TO INSTRUCTIONS | 2010 |
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RU2562430C2 |
| RUNTIME DETERMINATION OF TRANSLATION FORMATS FOR ADAPTER FUNCTIONS | 2010 |
|
RU2556418C2 |
| TRANSLATION OF INPUT/OUTPUT ADDRESSES TO MEMORY ADDRESSES | 2010 |
|
RU2547705C2 |
| ARCHITECTURAL MODE CONFIGURATION IN COMPUTING SYSTEM | 2015 |
|
RU2664413C2 |
| SEPARATE LOADING/STORAGE MEANS AND COMMAND THEREFOR | 2010 |
|
RU2554546C2 |
| COMMON BOOT SEQUENCE FOR CONTROL UTILITY ABLE TO BE INITIALISED IN MULTIPLE ARCHITECTURES | 2015 |
|
RU2665238C2 |
| MULTIPLEXOR CHANNEL | 0 |
|
SU1167613A1 |
| SAVING/RESET OF SELECTED REGISTERS AT TRANSACTION PROCESSING | 2012 |
|
RU2562424C2 |
| MEMORY ADDRESSING DEVICE | 0 |
|
SU1520528A1 |
