DEVICE FOR CONTROLLING FIRST STAGE OF ELECTRONIC NON-DISSIPATING LOAD Russian patent published in 2010 - IPC G01R1/40 

FIELD: physics.

SUBSTANCE: in the two-stage structure of the proposed electronic non-dissipating load, the first stage (DC-DC converter) is based on a transformer with a choke at the input. For reliable operation of the switch of the first stage and the entire electronic non-dissipating load, operation takes place in two modes, namely: start-up mode, when voltage at the output capacitor of the first stage increases to a given level, and operation mode, when energy from the output of the converter under analysis is transmitted through an electronic non-dissipating load to its input. The technical result of the invention is ensuring operation of the switch of the first stage in start-up mode and operation mode. Devices which ensure operation of the electronic non-dissipating load in start-up mode and operation mode comprise a microcontroller, field programmable logic device (FPLD) and an analogue pulse-duration modulation (PDM) controller, which interact with each other while providing operation of the first stage. The electronic non-dissipating load operates in two main modes: start-up mode; operation mode. The start-up mode is realised through smooth stretching of pulses transmitted to gates of the transistor bridge of the first stage. In start-up mode, the PDM controller if the first stage is switched on, clock pulses are generated by the microcontroller, where the said clock pulses are control pulses for each diagonal of the bridge cascade of the first stage. Pulses of the microcontroller are smoothly stretched at a given rate and, using control pulses, the FPLD generates pulses which are transmitted to drivers of the power part. At the start-up step, transistors of the first stage are switched off by about 20 ms, after which control of power switches of the first stage shifts to the FPLD for operation in shut-off mode. Start-up continues and voltage across the storage capacitor continues to rise. Once it reaches a preset value (360 V), the mode switches to operation mode. Switches of the first stage now operate with very low shut-off, maintaining voltage across the storage capacitor. In the operation mode, pulses from the secondary control end are transmitted to the microcontroller, which results in a reference sinusoidal current signal generated by the microcontroller being transmitted from the primary control end to the secondary control end for operation of an inverter which is in the power part of the second stage. Therefore, the first stage can now transmit energy through the inverter to the converter under analysis. In operation mode, the microcontroller transmits two short pulses whose frequency is four times greater than operating frequency of the power transformer to the FPLD. Also the FPLD generates intermediate clock pulses after receiving the said pulses from the microcontroller. The front of clock pulses forms the front of pulses of the power switches of the bridge and the trailing edge of pulses of the "PDM Signal" from the PDM controller forms the trailing edge of control pulses of switches of the bridge of the first stage. The filling coefficient of the "PDM Signal" can be equal to zero and hence in order to form the trailing edge of control pulses, clock pulse signals and the "PDM Signal" pass through an OR circuit.

EFFECT: duration of signals of control pulses for bridge switches in operation mode will change from minimum to maximum permissible.

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