FIELD: information technology.
SUBSTANCE: processing system may include multiple memory devices and multiple processors. Each of the processors is configured to generate memory access requests to one or more of the memory devices, with each of the memory access requests having an attribute that can be asserted to indicate a strongly-ordered request. The processing system further includes a bus interconnect configured to interface each of the processors to one or more memory devices, the bus interconnect being further configured to enforce ordering constraints on the memory access requests based on the attributes. The method describes operation of the said system.
EFFECT: broader functionalities.
20 cl, 4 dwg
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Authors
Dates
2010-11-27—Published
2006-03-23—Filed