ANALOGUE VOLTAGE MULTIPLIER Russian patent published in 2011 - IPC G06G7/16 H03F3/45 

FIELD: electricity.

SUBSTANCE: analogue voltage multiplier includes the first (1) (u_x) and the second (2) opposite phase sources of input voltage of channel "X", the first (3) (u_y3) and the second (4) (u_y4) sources of input voltage of channel "Y", the first (5) and the second (6) input transistors the emitters of which are combined and connected to the first (7) current-stabilising bipole connected through the second output to the first (8) supply voltage source, the third (9) and the fourth (10) input transistors the emitters of which are combined and connected to the second (11) current-stabilising bipole connected through the second output to the first (8) power source, load circuit (12) connected to the second (13) power source, as well as the first (14) and the second (15) outputs of the device. At that, bases of the second (6) and the third (9) input transistors are combined, base of the first (5) input transistor is connected to the first (1) (u_x) source of input voltage of channel "X"; collector of the first (5) input transistor is connected to the first (14) output of the device, collector of the fourth (10) input transistor is connected to the second (15) output of the device. To the circuit there introduced is the fifth (16), the sixth (17), the seventh (18) and the eighth (19) input transistors, emitters of the fifth (16) and the sixth (17) input transistors through the third (20) current-stabilising bipole are connected to the first (8) power source, emitters of the seventh (18) and the eighth (19) input transistors through the fourth (21) current-stabilising bipole are connected to the first (8) power source, bases of the second (6) and the third (9) input transistors are connected to the first (3) input voltage source (u_y3) of channel "Y", bases of the sixth (17) and the seventh (18) input transistors are combined and connected to the second (4) input voltage source (u_y4) of channel "Y", base of the fifth (16) input transistor is connected to base of the first (5) input transistor, base of the eighth (19) input transistor is connected to base of the fourth (10) input transistor and the second (2) input voltage source of channel "X", collectors of the second (6), the third (9), the sixth (17) and the seventh (18) input transistors are connected to output of additional voltage source (22), collector of the fifth (16) input transistor is connected to the second (18) output of the device, collector of the eighth (19) input transistor is connected to the first (14) output of the device.

EFFECT: decreasing supply voltage.

7 cl, 17 dwg