ANALOGUE VOLTAGE MULTIPLIER WITH LOW-VOLTAGE POWER SUPPLY Russian patent published in 2011 - IPC H03F3/45 G06G7/16 

FIELD: radio engineering.

SUBSTANCE: invention can be used in automatic amplification control devices, phase detectors and modulators, as well as in phase automatic frequency control and multiplication systems or as amplifier, transmission ratio as to voltage of which depends on control signal level. Analogue multiplier of voltages includes the first (1) (u_x) and the second (2) opposite phase sources of input voltage of channel "X", source (3) (u_y) of input voltage of channel "Y", the first (4) and the second (5) input transistors the emitters of which are combined and connected to the first (6) current-stabilising bipole connected through the second output to the first (7) supply voltage source (SVS), the third (8) and the fourth (9) input transistors emitters of which are combined and connected to the second (10) current-stabilising bipole connected through the second output to the first (7) supply voltage, load circuit (11) connected to the second (12) power supply, as well as the first (13) and the second (14) outputs of the device, collectors of the first (4) and the third (8) input transistors are connected to the first (13) output of the device, collectors of the second (5) and the fourth (9) input transistors are connected to the second (14) output of the device; at that, bases of the second (5) and the third (8) input transistors are combined, and base of the first (4) input transistor is connected to the first (1) (u_x) source of input voltage of channel "X". To the circuit there introduced is the fifth (15), sixth (16), seventh (17) and eight (18) input transistors, emitter of the fifth (15) and the sixth (16) input transistors through the third (19) current-stabilising bipole are connected to the first (7) power supply, emitters of the seventh (17) and eighth (18) input transistors through the fourth (20) current-stabilising bipole are connected to the first (7) power supply, bases of the second (5) and the third (8), sixth (16) and seventh (17) input transistors are connected to the first (3) input voltage source u_y of channel "Y"; base of the fifth (15) input transistor is connected to base of the first (4) input transistor; base of the eighth (18) input transistor is connected to base of the fourth (9) input transistor and the second (2) source of opposite phase input voltage of channel "X"; collectors of the fifth (15) and the seventh (17) input transistors are connected to the second (14) output of the device; collectors of the sixth (16) and the eighth (18) input transistors are connected to the first (13) output of the device.

EFFECT: reducing supply voltage.

4 cl, 7 dwg