MEMORY CONTROL FOR HIGH-SPEED CONTROL OF ACCESS TO ENVIRONMENT Russian patent published in 2011 - IPC H04L12/28 H04L12/56 

FIELD: information technologies.

SUBSTANCE: buffer of packets may store packets with the first data structure, comprising a packet length, a serial number and an indicator to the second data structure. Packet data may be saved in a coherent list of one or more second data structures. Queues of transmission and reception may be formed using coherent lists or arrays of the first data structures. Locations in the memory for storage of the first and second data structures may be maintained in the lists, which specify free locations for appropriate types of data structures. Flexible architecture of memory is described, where it is possible to select two configurations. In the first configuration the first memory includes parametres of each flow for multiple flows, and the second memory comprises a buffer of packets. In the second configuration the first memory comprises indicators for each flow at parametres for each flow in the second memory. The buffer of packets is located in the third memory. Various other aspects are also provided.

EFFECT: efficient high-speed control of access to medium.

21 cl, 62 dwg