FIELD: information technology.
SUBSTANCE: in one versions, the processor has an indicator of the current instruction set processing mode, data storage which is configured to store the indicator of the target instruction set processing mode, an execution unit which is configured to execute instructions according to the current instruction set processing mode, and a comparator circuit which is configured to compare the current instruction set processing mode with and the target instruction set processing mode when executing each instruction and indicate whether the current instruction set processing mode corresponds to the target instruction set processing mode.
EFFECT: high efficiency of debugging instructions in a processor.
28 cl, 3 dwg, 2 tbl
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