FIELD: information technology.
SUBSTANCE: in the known device containing shift registers, transposition forming unit (TFU), read-only memory unit, best version storage unit (BVSU), switch, ALU, arc selection decoder, reversible cell counter, random access memory unit, topology counter, distance counters, multiplier, adder, register of minimum connections length, comparison elements, subtractor, count start trigger, mode trigger, topology assignment trigger, connections length register, arc counter, arc locking decoder, arc number register, minimum weight register, electronic graph model, group of 1-st to n-th OR gates, group of 1-st to m-th AND gates, AND gates, OR gates units, univibrators, delay elements, the lower score generator is introduced. This generator contains matrix of (i,j) (i=1,2, …, m; j=1,2,…, n) adders, the first and the second row counters, the first and the second column counters, matrix of ((i,j) (i=1,2,…,m; j=1,2,…,n) registers, the first and the second decoders of horizontally fixed arcs, the first and the second decoders of vertically fixed arcs, matrix of (i,j) (i=1,2,…,m; j=1,2,…,n) OR gates, the first {(i,j) (i=1, 2,…,m; j=1,2,…,n) and the second (i,j) (i=1,2,…,m; j=1,2,…,n) matrices of AND gates, the first and the second delay elements, the first and the second incident vortex counter, the first and the second OR gates.
EFFECT: wider field of the device application due to introduction of search facilities for lower score of weighted graphs location in matrix topology model with bidirectional data transfer by a criterion of minimising intensity of processes and data interaction.
2 cl, 4 dwg
